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STK1743
nvTimeTM 8K x 8 AutoStoreTM nvSRAM with Real-Time Clock
ADVANCE
FEATURES
* Data Integrity of Simtek nvSRAM Combined with Full-Featured Real-Time Clock * Stand-Alone Nonvolatile Memory and TimeKeeping Solution--No Other Parts Required * No Batteries to Fail * Fast 25ns, 35ns and 45ns Access Times * Software- and AutoStoreTM-Controlled Nonvolatile Cycles * Year 2000 Compliant with Leap Year Compensation * 24-Hour BCD Format * 100-Year Data Retention over Full Industrial Temperature Range * Full 30-Day RTC Operation on Each Power Loss * Single 5V 10% Power Supply
DESCRIPTION
The Simtek STK1743 DIP module houses 64Kb of nonvolatile static RAM, a real-time clock (RTC) with crystal and a high-value capacitor to support systems that require high reliability and ease of manufacturing. READ and WRITE access to all RTC functions and the memory is the same as a conventional x 8 SRAM. The highest eight addresses of the RAM support clock registers for centuries, years, months, dates, days, hours, minutes and seconds. Independent data resides in the integral EEPROM at all times. Automatic RECALL on power up transfers the EEPROM data to the SRAM, while an automatic STORE on power down transfers SRAM data to the EEPROM. A software RECALL and STORE are also possible on user command. nvTimeTM allows unlimited accesses to SRAM, unlimited RECALLs and 106
STOREs.
BLOCK DIAGRAM
EEPROM ARRAY 128 x 512 ROW DECODER VCC STORE/ RECALL CONTROL
PIN CONFIGURATIONS
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
A5 A6 A7 A8 A9 A11 A12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
STORE STATIC RAM ARRAY 128 x 512 RECALL
POWER CONTROL
SOFTWARE DETECT
A0 - A12
VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
600 mil Dual In-Line Module
INPUT BUFFERS
COLUMN I/O COLUMN DEC
RTC
PIN NAMES
A0 - A12 W Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground
A0 A1 A2 A3 A4 A10
MUX
A0 A12 G E W
DQ0 - DQ7 E G VCC VSS
March 1999
7-1
STK1743
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to VSS . . . . . . . . . .-0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC b
1
(VCC = 5.0V 10%)
INDUSTRIAL UNITS MIN MAX 85 80 75 6 15 4 30 26 23 3 1 5 2.2 VSS - .5 2.4 0.4 0 70 - 40 VCC + .5 0.8 2.2 VSS - .5 2.4 0.4 85 MIN MAX 95 85 80 7 15 4 31 27 24 3 1 5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA A A V V V V C tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels All Inputs Don't Care tAVAV = 25ns, E V IH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA NOTES
PARAMETER Average VCC Current
ICC c
2 3
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns Average VCC Current during AutoStoreTM Cycle Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
ICC
b
ICC c
4
ISB d
1
ISB d
2
IILK IOLK VIH VIL VOH VOL TA
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained at minimum cycle with outputs unloaded. 1 3 Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . .1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
CAPACITANCEe
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 10 12 UNITS pF pF CONDITIONS
OUTPUT 255 Ohms
V = 0 to 3V V = 0 to 3V
30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 1999
7-2
STK1743
READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCL
d, e
(VCC = 5.0V 10%)
STK1743-25 STK1743-35 MIN MAX 35 35 25 10 5 5 10 0 10 0 25 0 35 0 13 0 45 5 5 13 0 15 35 15 5 5 15 45 45 20 STK1743-45 UNITS MIN MAX 25 25 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage.
READ CYCLE #1: Address Controlledf, g
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT) DATA VALID 3 tAVQV
READ CYCLE #2: E Controlledf
2 tAVAV ADDRESS 6 E tELQX 7 tEHQZ 1 tELQV 1 1 tEHICCL
G 4 tGLQV 9 tGHQZ
8 tGLQX DQ (DATA OUT) 10 tELICCH
DATA VALID
ACTIVE
ICC
STANDBY
March 1999
7-3
STK1743
WRITE CYCLES #1 & #2
SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZh, i tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 PARAMETER MIN 25 20 20 10 0 20 0 0 10 5 MAX MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns STK1743-25
(VCC = 5.0V 10%)
STK1743-35 STK1743-45 UNITS
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions.
WRITE CYCLE #1: W Controlledj
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ
PREVIOUS DATA DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
DATA OUT
HIGH IMPEDENCE
21 tWHQX
WRITE CYCLE #2: E Controlledj
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDENCE
DATA IN DATA OUT
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STK1743
AutoStoreTM / POWER-UP RECALL
SYMBOLS NO. Standard 22 23 24 25 26 tRESTORE tSTORE tDELAY VSWITCH VRESET Power-Up RECALL Duration PARAMETER MIN MAX 550 10 1 4.0 4.5 3.9 s ms s V V k g g
(VCC = 5.0V 10%)
STK1743 UNITS NOTES
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level
Note k:
tRESTORE starts from the time VCC rises above VSWITCH.
AutoStoreTM / POWER-UP RECALL
VCC
5V 25 VSWITCH 26 VRESET
AutoStoreTM
23 tSTORE
POWER-UP RECALL 22 tRESTORE W DQ (DATA OUT)
24 tDELAY
POWER-UP RECALL
BROWN OUT NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET )
BROWN OUT AutoStoreTM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStoreTM
RECALL WHEN VCC RETURNS ABOVE VSWITCH
March 1999
7-5
STK1743
SOFTWARE MODE SELECTION
E W A12 - A0 (hex) 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z NOTES
L
H
l
L
H
l
Note l:
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE CYCLES #1 & #2m, n
SYMBOLS NO. #1 27 28 29 30 31 tAVAV tAVEL
m m
(VCC = 5.0V 10%)
STK1743-25 STK1743-35 MIN 35 0 25 20 20 20 MAX STK1743-45 UNITS MIN MAX MIN 45 0 30 20 20 MAX ns ns ns ns s 25 0 20 20
PARAMETER
STORE/RECALL Initiation Cycle Time
Address Set-up Time Clock Pulse Width Address Hold Time
tELEH tELAX
g, m
tRECALL
RECALL Duration
Note m: The software sequence is clocked with E controlled reads. Note n: The six consecutive addresses must be in the order listed in the Software Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE CYCLE: E Controlled
tAVAV ADDRESS
ADDRESS #1 27
tAVAV
ADDRESS #6
27
tAVEL E
28
tELEH
29
tELAX tSTORE tRECALL DQ (DATA OUT)
DATA VALID DATA VALID HIGH IMPEDENCE 23
30
/
31
March 1999
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STK1743
DEVICE OPERATION
The STK1743 is an 8K x 8 nonvolatile static RAM with a full-function real-time clock (RTC). The data integrity is secured in EEPROM, not subject to battery or capacitor discharge. The real-time clock registers reside in the eight uppermost RAM locations, and contain century, year, month, date, day, hour, minute and second data in 24-hour BCD format. Corrections for the day of the month and leap years are made automatically. This nonvolatile time-keeping RAM is functionally similar to any JEDEC standard 8K x 8 SRAM. The RTC registers are double-buffered to avoid access of incorrect data that could otherwise occur during clock update cycles. The double-buffered system prevents time loss by maintaining internal clock operation while time register data is accessed. The STK1743 contains integral power-fail circuitry that deselects the device when VCC drops below VSWITCH. The STK1743 is a pin-compatible replacement for the ST Microelectronics M48T08 and the Dallas Semiconductor DS1743, but without the limitations of an embedded lithium battery. The Simtek device uses a double-layer high-value capacitor to maintain RTC operation on power down for at least 30 days. The part can be soldered directly onto printed circuit boards and handled without concern for damaging or discharging internal batteries. Unlike some other RTCs, the STK1743 is Year 2000-compliant.
NOISE CONSIDERATIONS
Note that the STK1743 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM AND RTC READ
The STK1743 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W is brought low. Note that the eight most significant bytes of the address space are reserved for accessing the RTC registers, as shown in the Register Map below. While the double-buffered RTC register structure reduces the chance of reading incorrect data from the clock, the user should halt internal updates to the
RTC REGISTER MAP
ADDRESS (HEXADECIMAL) 1FF8 1FF9 1FFA 1FFB 1FFC 1FFD 1FFE 1FFF Key: R W 1 FT X BCD DATA FUNCTION/RANGE D7 W X X X 1 X X X FT X X 10 Years = Read Bit = Write Bit = Battery Flag High (no battery to fail) = Frequency Test Bit = Don't Care X X 10 Dates 10 Mos. D6 R D5 D4 D3 D2 Centuries Seconds Minutes Hours X X Days Dates Months Years D1 D0 Centuries: 00-39, Control Seconds: 00 - 59 Minutes: Hours: Days: Dates: Months: Years: 00 - 59 00 - 23 01 - 07 01 - 31 01 - 12 00 - 99 10 Centuries 10 Seconds 10 Minutes 10 Hours
March 1999
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STK1743
STK1743 clock registers before reading clock data to prevent reading of data in transition. Stopping the internal register updates does not affect clock accuracy. The updating process is stopped by writing a "1" to the read bit (the seventh most significant bit in the control register), and will not restart until a "0" is written to the read bit. The RTC registers can then be read while the internal clock continues to run. Within one second after a "0" is written to the read bit, all STK1743 registers are simultaneously updated. write protection occurs), access to the internal clock register and the SRAM is blocked. At this voltage, SRAM data is automatically stored to the integral EEPROM, and power for the clock oscillator switches from the VCC pin to the internal capacitor. The capacitor maintains clock activity and data until VCC returns to its nominal level.
SOFTWARE NONVOLATILE STORE
The STK1743 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
SRAM WRITE AND SETTING THE CLOCK
A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. Setting the write bit (the eighth most significant bit of the control register) to a "1" halts updates to the STK1743 registers. The correct day, date and time can then be written into the registers in 24-hour BCD format. Resetting the write bit to "0" transfers those values to the actual clock counters, after which the clock resumes normal operation.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the memory accesses will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
CLOCK ACCURACY
The STK1743 is guaranteed to be accurate to within 1 minute per month at 25C. The part requires no additional calibration, and temperature variations will have a negligible effect in most applications.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed:
DATA RETENTION MODE
During normal operation (VCC 4.5V), the STK1743 can be accessed with standard SRAM READ and WRITE cycles. However, when VCC falls below the power-fail voltage, VSWITCH (the voltage at which
March 1999
7-8
STK1743
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
latched. When VCC once again exceeds VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete.
HARDWARE PROTECT
The STK1743 offers hardware protection against inadvertent STORE and SRAM WRITE operation during low-voltage conditions. When VCC < VSWITCH, all software STORE operations and SRAM writes are inhibited.
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Note that the RTC registers are not affected by nonvolatile operations.
LOW AVERAGE ACTIVE POWER
The STK1743 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK1743 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading.
AutoStoreTM OPERATION
The STK1743 uses capacitance built into the module to perform an automatic STORE on power down. In order to prevent unnecessary STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether a WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition (VCC < VRESET), an internal recall request will be
100
100
Average Active Current (mA)
Average Active Current (mA)
80
80
60
60 TTL CMOS 20
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
40
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
March 1999
7-9
STK1743 ORDERING INFORMATION
STK1743 - D 25 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
25 = 25ns 35 = 35ns 45 = 45ns
Package
D = 600 mil Dual In-Line Module
March 1999
7-10

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